Instantiating pipeline multiplier, warning

[lingqi0077]

im trying instantiating pipeline multiplier of designware to solve my design's timing violations,but when synthesizing, DC report many warnings as below:

Warning: The following cells only drive asynchronous pins of sequential cells which have no timing constraint. Therefore retiming will not optimize
delay through them:
mult6/*cell*39538 (CLKBUFX20TF)
mult6/*cell*39536 (CLKBUFX20TF)
mult6/*cell*39537 (CLKBUFX20TF)
mult6/*cell*39535 (CLKBUFX20TF)
mult6/*cell*39533 (CLKBUFX20TF)
mult6/*cell*39534 (CLKBUFX20TF)
mult6/*cell*39531 (CLKBUFX20TF)
mult6/*cell*39532 (CLKBUFX20TF)
mult6/*cell*28602 (CLKINVX12TF)

what's the reason of these warnings? and how to resolve it?

 

[kornukhin]

Re: plz help,about DC warnings

Is this RTDC-115 warning? If so, did you constraint all of your asynchronous pins of sequential cells?

 

[lingqi0077]

Re: plz help,about DC warnings

i dont know what is RTDC-115
and how to constraint asynchronous pins of sequential cells?? should i set what kinds of constraint on these pins?

 

[kornukhin]

Re: plz help,about DC warnings

In Synopsys On-Line Documentation every error&warning have their own code. Here is RTDC-115 description from SOLD:

RTDC-115 (warning) The following cells only drive asynchronous pins of sequential cells which have no timing constraint. Therefore retiming will not optimize delay through them:
DESCRIPTION
This warning message occurs when any paths to asynchronous cells of sequential cells
do not have timing constraints. Therefore, retiming does not include cells on these
paths that only drive such pins into the retiming optimization.
WHAT NEXT
This is a warning message only. No action is required on your part.
SEE ALSO
balance_registers, (2), optimize_registers (2).

You can also read "Design Compiler Reference Manual: Register Retiming" for additional information about DC conatraints requirements.

 

[lingqi0077]

Re: plz help,about DC warnings

In Synopsys On-Line Documentation every error&warning have their own code. Here is RTDC-115 description from SOLD:

RTDC-115 (warning) The following cells only drive asynchronous pins of sequential cells which have no timing constraint. Therefore retiming will not optimize delay through them:
DESCRIPTION
This warning message occurs when any paths to asynchronous cells of sequential cells
do not have timing constraints. Therefore, retiming does not include cells on these
paths that only drive such pins into the retiming optimization.
WHAT NEXT
This is a warning message only. No action is required on your part.
SEE ALSO
balance_registers, (2), optimize_registers (2).

You can also read "Design Compiler Reference Manual: Register Retiming" for additional information about DC conatraints requirements.

thx for help , seems like i need to learn more about DC

 

[rakko]

Re: plz help,about DC warnings

Or you can set a false path on all of these if you want to keep your log file clean and document your work properly.