Junior Member level 1
I wrote a couple of Verilog modules, one a generic multiplexer with parameter (nmBits) passed into it and the other that instantiates it with value 2, and included those two modules in file "UmM.v":
Then I wrote a module to test it and put both files into EDA Playground. When I clicked on <Run>, I got told:
Can anyone tell me what I'm doing wrong? Why won't this compile?
module Mux #( nmBits = 1) ( result, control, hgVal, lwVal); output [ nmBits-1:0] result; input control; input [ nmBits-1:0] hgVal; input [ nmBits-1:0] lwVal; genvar bt; generate for (bt = 0; bt < nmBits; bt = bt + 1) begin assign result[ bt] = control ? hgVal[ bt] : lwVal[ bt]; end endgenerate endmodule module UseMux( rslt, cntrl, hVal, lVal); output [ 1:0] rslt; input cntrl; input [ 1:0] hVal; input [ 1:0] lVal; Mux mx2 #(2)( rslt, cntrl, hVal, lVal); endmodule
Parsing design file 'design.sv' Error-[UTOPN] Unknown type or port name The type name 'Mux' is unknown, or the identifier 'mx2' has not been listed as a port, or the declaration might represent an instance missing parentheses. "design.sv", 24 Source info: Mux mx2 #(2)( rslt, cntrl, hVal, lVal); Error-[SE] Syntax error Following verilog source has syntax error : "design.sv", 24 2 errors CPU time: .173 seconds to compile Exit code expected: 0, received: 1 Done