terranpro
Newbie level 4
Hi,
I'm beginning VLSI student working on a 16-bit simplified datapath design. I have bitslice instances that I need to instantiate and array, but I do not wish to make control line connections for each part - I'd like to become proficient with the cadence tools.
From reading the manual and experimenting, I see that I can make instance names using X<0:15> to create an array of instances in the schematic, and connections only one time.
This will work great for part of my design, but for my adder bitslice, I need the carry out (Ci+1) of bit 0 to propagate to Ci of bit 1, and so on. What is the recommended way of handling this ? If I have to make splits in my instance arrays, how can I tap a single bit from a bus line and route it to the single bit instances? Any connection made to a net results in a single net?
I've posted a screen shot in hopes it may clarify.
Thanks,
Brian
P.S. also posted image @ https://tinypic.com/view.php?pic=30981fp&s=5
*** Notes on Image ***
The decoder contains all my control lines for accessing the 4 register (16bit per reg) register file. WDk, Ai, and Bi, are all 16bits.
fastadder_1x Ci (carry in) and Ci+1 (carry out) are the nets I'm asking about
I tried to connect Ci+1 to Ci and use Create Wire Name to somehow connect these? (Say Gnd => Ci<0>, Ci+1<0:14> => Ci<1:15>, Ci+1 => outpin) ?
I'm beginning VLSI student working on a 16-bit simplified datapath design. I have bitslice instances that I need to instantiate and array, but I do not wish to make control line connections for each part - I'd like to become proficient with the cadence tools.
From reading the manual and experimenting, I see that I can make instance names using X<0:15> to create an array of instances in the schematic, and connections only one time.
This will work great for part of my design, but for my adder bitslice, I need the carry out (Ci+1) of bit 0 to propagate to Ci of bit 1, and so on. What is the recommended way of handling this ? If I have to make splits in my instance arrays, how can I tap a single bit from a bus line and route it to the single bit instances? Any connection made to a net results in a single net?
I've posted a screen shot in hopes it may clarify.
Thanks,
Brian
P.S. also posted image @ https://tinypic.com/view.php?pic=30981fp&s=5
*** Notes on Image ***
The decoder contains all my control lines for accessing the 4 register (16bit per reg) register file. WDk, Ai, and Bi, are all 16bits.
fastadder_1x Ci (carry in) and Ci+1 (carry out) are the nets I'm asking about
I tried to connect Ci+1 to Ci and use Create Wire Name to somehow connect these? (Say Gnd => Ci<0>, Ci+1<0:14> => Ci<1:15>, Ci+1 => outpin) ?
