input signal is never used problem

[yburake]

hi,


i have device xilinx spartan 3e-100 cp132 . i have 128mhz main clock.

"
process(multplefreq)
begin
if rising_edge(multplefreq) then
counter <= counter+1;
if counter<=0 then
output<='0';
end if;
if counter<=1 then
output<='1' ;
end if;
if selection="00" then
if (counter=15) then
counter <= 0;
end if;
end if;
if selection="01" then
if (counter=31) then
counter <= 0;
end if;
end if;
if selection="10" then
if (counter=63) then
counter <= 0;
end if;
end if;
if selection="11" then
if (counter=127) then
counter <= 0;
end if;
end if;
end if;
end process;


finalout<= output or allpass ;

end Behavioral;
"

altough i use both allpass and selection, i always get these warnings,

WARNING:Xst:647 - Input <selection> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <allpass> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

and when i embed the code(of course i changed the selection buttons) , the device always does this if;
if selection="00" then
if (counter=15) then
counter <= 0;
end if;
end if;

so that the frequency is not a selection. how can i solve this warning.(yes i need an asymmetric output clock the pulse width has to be same all frequencies)

regards
Burak

 

[sanju_]

refer this may be helpful...
**broken link removed**
**broken link removed**
https://www.edaboard.com/threads/152846/

 

[TrickyDicky]

You have only posted a code snippet. What about the rest of the code?

 

[permute]

counter starts at 0.
output will be set to 0 if counter is less than or equal to zero. However, if counter is less than or equal to 1, it will be set to 1. in other cases, output will remain in its previous state. Thus output = 1. ( x <= 0 implies x <= 1)
final output is output (1) or allpass (?). thus finaloutput = 1.

counter can do whatever it wants. it doesn't affect anything. As a result, the selection input isn't needed. allpass is or'd with 1 to get the finaloutput, and thus isn't really needed.

 

[TrickyDicky]

If you'd have used elsif instead of just ifs all the time, it might not have happened.

 

[mrflibble]

counter can do whatever it wants. it doesn't affect anything. As a result, the selection input isn't needed. allpass is or'd with 1 to get the finaloutput, and thus isn't really needed.

Precisely. Just because you "have included a signal somewhere in your logic" != "signal is NEEDED for evaluation of the logic function". As soon as the synthesizer is able to optimize away some signals, it will do so. And rightfully so. So when the evaluation of a function is independant of some input XYZ, it will try to optimize away that XYZ.

And it looks that is the case with your current code...