Hi ~Sam,
Thank you for your reply. On point 1 the input constraints, I'm not sure I understand how they are asynchronous. The inputs are 5 bits parallel. The modules I will be using are in the attachment (I will use the 7Gb/s generator module) so these generate this data on the rythm of the CLK which will also drive the chip. But from the datasheet it seems that these generators have great capabilities in setting delays. So inputs will definitely be clocked, but the delays can be adjusted. That is why I am unsure about what the input delay constraint is, as this is the time needed for the signal to travel from the generator -> SMA cables -> PCB -> bondwires up to the first flop. If path length's are somewhat equal I guess they will arrive practically at the same moment. But then again, I can delay e.g. the clock as I need to make sure the setup time of the first flop is respected if this makes sense? So I think I can safely set the minimal input delay constraint zero (meaning clock & data arrive at the same moment) and I can set the the maximum input delay to a value of how much I would like to delay the clock, maybe 1/2 of a period?
For the output I am wondering if there are special constraints to keep the skew between the digital outputs minimal ? (as they will toggle my transistors preferably at exactly the same time to limit glitches) I can further take care the path lengths in the routing between the digital & analog block, but the skew on the digital should already be minimal for this to have any effect. Any ideas for this?