Hey, I want to input a n*m (n and m are defined) matrix in verilog (where each element is of 32 bit length), but the compiler gives an error. Is there any direct way to do so? I don't want to write n*m separate input elements.
Verilog is now a subset of SystemVerilog.
At least in SystemVerilog, you can:
PHP:
input reg [0:9][0:12][31:0] matrix ;
This will give you a 10*13 matrix, in which each element is 32 bit register.
if you define it as row=10, column=13, then matrix[2][3] means the element at row[2] and column[3].