Input matrix in verilog

[akipro]

Hey, I want to input a n*m (n and m are defined) matrix in verilog (where each element is of 32 bit length), but the compiler gives an error. Is there any direct way to do so? I don't want to write n*m separate input elements.

This is what I tried:

 input reg [31:0] matrix [0:9][0:12]

Anything wrong here?

Thanks

 

[ads-ee]

Verilog doesn't support arrays in the module port declaration. You'll need to concatenate the busses together.

Input [10*13*32-1:0] matrix

In the body of your code you can include a for loop to extact slices and assign them to a wire array.

reg cannot be used as the type for an input.

Regars

 

[akipro]

Can I use verilog code in system verilog, it seems we can use 2D matrix as input in system verilog?

 

[ads-ee]

I'm not sure as I mostly use Verilog. I can't check as I don't have the IEEE spec handy. You can download it for free on IEEE's we site.

 

[rberek]

For the most part System Verilog is backwards compatible with Verilog

 

[layowblue]

Verilog is now a subset of SystemVerilog.
At least in SystemVerilog, you can:

input reg [0:9][0:12][31:0] matrix ;

This will give you a 10*13 matrix, in which each element is 32 bit register.
if you define it as row=10, column=13, then matrix[2][3] means the element at row[2] and column[3].