Input capacitance of combination gate

[rain_181914]

For one nand2 gate, I run simulation(use lx(m)) and get the capacitances of two input ports.
After I check two different standardcell libraries, There are two different result.(PMOS size of A and B are equal. NMOS size of A and B are equal too)
One , Input capacitance of A is bigger than B.
The other, Input capacitance of B is bigger than A.

So, I wonder know that which capacitance is a bigger one and why ?

 

[santuvlsi]

Dear dude,

Normally the PMOS should be 2 or 3 times bigger then nmos.

both cant be equal. if it is equal the rise time and fall tme will not be the same.

so the switching point will be not at 1/2 of VDD.

of course the capacitacne will vary if u shift from one statndard library to other, because standard cell are technology depenedent, like 90nm,130nm.


Hope u got

Santu

 

[rain_181914]

dear,

I think, maybe you didn't unstandard what I said.

Cap A = Cap pmos A port + Cap nmos A port.

e.g.
pmos A : l=0.25 w＝2
pmos B : l=0.25 w＝2
nmos A : l=0.25 w＝1
nmos B : l=0.25 w＝1

 

[onlymusic16]

dear,

I think, maybe you didn't unstandard what I said.

Cap A = Cap pmos A port + Cap nmos A port.

e.g.
pmos A : l=0.25 w＝2
pmos B : l=0.25 w＝2
nmos A : l=0.25 w＝1
nmos B : l=0.25 w＝1

The libraries come up with these capacitances only after the completion of the layout, the difference would probably be in the layout.

Accordingly, if you see in the layout in the first case, A would have a larger "route cap" than B and vice versa for the second case.

To check this, use the simulator to report the caps for the two circuits.

Channel caps would be same but the route caps will be different and finally, its the channel cap + route cap that you see in the .lib.

Hope it helps!!!

 

[rain_181914]

Dear onlymusic16,

The two parasitic capacitances of two port are different in .lib file.

But parasitic capacitances of A port - parasitic capacitances of B port = 0.02pf
Input capacitances of A port - Input capacitances of B port =0.5pf

I have defined AS, AD, PD and PS in .sp file When I run Hspice which transfer mos model.


Pls help

 

[onlymusic16]

Dear onlymusic16,

The two parasitic capacitances of two port are different in .lib file.
Pls help

Open the layout and try to figure out why the parasitic caps are different. Your answer lies there, not in the .lib file.

 

[rain_181914]

Sorry, I want to explain that parasitical capacitance is in .cir file.

I checked two values of two input paracitical capacitance.
parasitic capacitances of A port - parasitic capacitances of B port = 0.02pf

But from .lib file, Input capacitances of A port - Input capacitances of B port =0.5pf

so I fell that it is unfeasible for this explanation.