Jul 9, 2011 #1 J jakyshan1990 Junior Member level 2 Joined Mar 10, 2011 Messages 22 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,393 how to connect 2 inout ports 1st port is declaring in block named by memory 2nd port is declaring in block named by control
how to connect 2 inout ports 1st port is declaring in block named by memory 2nd port is declaring in block named by control
Jul 9, 2011 #2 I Iamventure Junior Member level 3 Joined Jun 6, 2007 Messages 30 Helped 7 Reputation 14 Reaction score 5 Trophy points 1,288 Activity points 1,451 Join them in port map directly. It works when I connected a top level inout port to inout port of two components inside it.
Join them in port map directly. It works when I connected a top level inout port to inout port of two components inside it.
Jul 9, 2011 #3 H hossam abdo Full Member level 2 Joined Mar 13, 2011 Messages 122 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,298 Location Alexandria, Egypt, Egypt Activity points 2,064 i did this really but there is error appear -- that the signal which connect between them has multiple driver
i did this really but there is error appear -- that the signal which connect between them has multiple driver
Jul 9, 2011 #4 I Iamventure Junior Member level 3 Joined Jun 6, 2007 Messages 30 Helped 7 Reputation 14 Reaction score 5 Trophy points 1,288 Activity points 1,451 hossam abdo said: i did this really but there is error appear -- that the signal which connect between them has multiple driver Click to expand... Hi did you try directly giving the port name of one component into the other without the signal?
hossam abdo said: i did this really but there is error appear -- that the signal which connect between them has multiple driver Click to expand... Hi did you try directly giving the port name of one component into the other without the signal?
Jul 9, 2011 #5 H hossam abdo Full Member level 2 Joined Mar 13, 2011 Messages 122 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,298 Location Alexandria, Egypt, Egypt Activity points 2,064 this can't be happen in structural modeling the port assigned must be defined in the top module . these are connected by signal only
this can't be happen in structural modeling the port assigned must be defined in the top module . these are connected by signal only
Jul 10, 2011 #6 G GiuseppeLaPiana Newbie level 5 Joined Jul 5, 2011 Messages 10 Helped 5 Reputation 10 Reaction score 5 Trophy points 1,283 Activity points 1,367 Could you post the snippet of VHDL you are having trouble with?