How to achieve controllability when pin is buss connection

[Varun124]

Hi Team,

I was working on TDF coverage analysis i am seeing once scenario. In of the hierarchy all the faults are unable to control and these are coming from buss connection. How ATPG tool detect faults when the controllability is coming from buss connection

Thanks in Advance

 

[maulin sheth]

Hi Team,

I was working on TDF coverage analysis i am seeing once scenario. In of the hierarchy all the faults are unable to control and these are coming from buss connection. How ATPG tool detect faults when the controllability is coming from buss connection

Thanks in Advance

Is your design has a lot of combo logic from INPUT to First flop?
If yes, then these will be covered in the chip level ATPG run because input ports are not controlled during our block level ATPG run, these are only controlled during the chip level run.