you23
Newbie level 3

I am testng sigma-delta modulator (SC) that I designed.
*2nd order - 1bit output(SC)
*fully-differential input
*fclk=500k
*gain=1
*VDD=3V, Vcommon=1.5V
in these case ,
1) Vinp=Vcommon, Vinm=0to3V swep ---> gain=almost 0, INL=4LSB
2) Vinm=0to3V, Vinm=Vcommon swep ---> gain=lower than 0
linerlity is different,
please tell me which point shold I check in circuit.
*2nd order - 1bit output(SC)
*fully-differential input
*fclk=500k
*gain=1
*VDD=3V, Vcommon=1.5V
in these case ,
1) Vinp=Vcommon, Vinm=0to3V swep ---> gain=almost 0, INL=4LSB
2) Vinm=0to3V, Vinm=Vcommon swep ---> gain=lower than 0
linerlity is different,
please tell me which point shold I check in circuit.