Inheritance of Clock in SV Sequence

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kunal1514

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Hi All,

A very interesting query i am having.

Can any body tell me that the below mentioned Sequence "Sequence1"
will inherit which clock either "src_clk" or "dst_clk".

As this "Property" contains two clocks.

Property
//--------------------------------------------

property clk_implication_example;
@(posedge src_clk) seq0 |=> @(posedge dst_clk) prop0;
endproperty

//---------------------------------------------

Sequence
//---------------------------------------------
sequence Sequence1;
~reset ##5 req;
endsequence

//---------------------------------------------

Explain it.

Regards
 

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