Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Inheritance of Clock in SV Sequence

Status
Not open for further replies.
K

kunal1514

Full Member level 1
Full Member level 1
Joined
Dec 13, 2006
Messages
98
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
2,027
Hi All,

A very interesting query i am having.

Can any body tell me that the below mentioned Sequence "Sequence1"
will inherit which clock either "src_clk" or "dst_clk".

As this "Property" contains two clocks.

Property
//--------------------------------------------

property clk_implication_example;
@(posedge src_clk) seq0 |=> @(posedge dst_clk) prop0;
endproperty

//---------------------------------------------

Sequence
//---------------------------------------------
sequence Sequence1;
~reset ##5 req;
endsequence

//---------------------------------------------

Explain it.

Regards
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top