infinite simulation loop in verilog

Status
Not open for further replies.
C

coolajnabee1

Newbie level 3
Joined
Jan 23, 2010
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,296
Hi every1, i am stuck at a problem, i am having an infinite simulation loop how to solve it

Any ideas, hints would be helpful.
 

Re: How would you create infinite simulation loop in verilog

you mean you want to have a state which can't be stoped , right?
 

Re: How would you create infinite simulation loop in verilog

yes that is correct

any ideas ??
 

Re: How would you create infinite simulation loop in verilog

In Verilog you can create infinite loop using forever, while blocks.

forever
begin
...
...
end

while(1)
begin
...
...
...
end

But you should be sure that you are using any time consuming statements inside a loop.
It can be delay operator #5 or event @(...).
Otherwise your simulation will be stopped.

Please remember code execution is sequential not parallel.

Bests,
Tiksan
 

Re: How would you create infinite simulation loop in verilog

Hey Syswip,

thanks for your help..
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…