infinite simulation loop in verilog

[coolajnabee1]

Hi every1, i am stuck at a problem, i am having an infinite simulation loop how to solve it

Any ideas, hints would be helpful.

 

[ljxpjpjljx]

Re: How would you create infinite simulation loop in verilog

you mean you want to have a state which can't be stoped , right?

 

[coolajnabee1]

Re: How would you create infinite simulation loop in verilog

yes that is correct

any ideas ??

 

[Syswip]

Re: How would you create infinite simulation loop in verilog

In Verilog you can create infinite loop using forever, while blocks.

forever
begin
...
...
end

while(1)
begin
...
...
...
end

But you should be sure that you are using any time consuming statements inside a loop.
It can be delay operator #5 or event @(...).
Otherwise your simulation will be stopped.

Please remember code execution is sequential not parallel.

Bests,
Tiksan

 

[coolajnabee1]

Re: How would you create infinite simulation loop in verilog

Hey Syswip,

thanks for your help..