Here's a Verilog inference example. The synthesis tool recognizes (infers) the 8-bit up-counter with synchronous clear, and generates an appropriate register with adder logic.
If you simply drop a "COUNTER" module from your synthesis tool's library into your HDL, that's instantiation. Of course, your library may not have a COUNTER module, or it may have a different name, or it may have different I/O signals.
inferring is the logic which tool generate automatically which you dont describe....
instantiation is the logic which tool generate which you describe....