It seems that (some?) synthesis tools do not allow us to infer TRUE Dual-Port RAM, eg: two independent read and write ports. Is there a particular reason for this? Do you know of any synthesis tools that actively supports this? I don't believe that either Altera Quartus II or Mentor PrecisionRTL does.. what about Xilinx ISE, or Synopsys DC-FPGA, etc.
Xilinx ISE doesn't infer true dual port RAMS either, at least not before ISE 6.1 which is the version I am currently using. I don't know why they cannot infer true dual port RAM, probably because not all the devices support this type of Memory.
That's clearly what they want us to do, but it's a pain in the @ss when you want to generate a parameterizable design. Design portability is also an important issue.
Xilinx Coregen allows you to generate true Dual Port RAMs. Seperate read and write ports. If you use coregen allows you to configure the dual port RAM for various sizes and other parameters.
Portability is still a problem since it will only work for Xilinx.