Inferring TRUE Dual-Port RAM ???

[ed271828]

inferring true dual port ram

Hi,

It seems that (some?) synthesis tools do not allow us to infer TRUE Dual-Port RAM, eg: two independent read and write ports. Is there a particular reason for this? Do you know of any synthesis tools that actively supports this? I don't believe that either Altera Quartus II or Mentor PrecisionRTL does.. what about Xilinx ISE, or Synopsys DC-FPGA, etc.

Thanks,

Ed

 

[mendozaulises]

xilinx inferring dual port ram

Xilinx ISE doesn't infer true dual port RAMS either, at least not before ISE 6.1 which is the version I am currently using. I don't know why they cannot infer true dual port RAM, probably because not all the devices support this type of Memory.

 

[freeinthewind]

fpga true dual port ram

maybe u should use the IPcore provided by FPGA vendors.

 

[bansalr]

synplify+dual true port

Synplify does infer True dual port RAMS. if u follow there coding guidelines.
Mentor precision doesn't

 

[ed271828]

inferring rams

maybe u should use the IPcore provided by FPGA vendors.

That's clearly what they want us to do, but it's a pain in the @ss when you want to generate a parameterizable design. Design portability is also an important issue.

 

[kochirojave]

what is true dual port ram

Xilinx Coregen allows you to generate true Dual Port RAMs. Seperate read and write ports. If you use coregen allows you to configure the dual port RAM for various sizes and other parameters.

Portability is still a problem since it will only work for Xilinx.