Inferring DSP48s(four slices) as 35x35 muliplier

[SharpWeapon]

Hi,

I want to INFER the DSP48 slice as a multiplier for large numbers, more than 25x18( I did this by instantiating), specifically 35x35. In UG193 page 71, it is described that to have 35x35 it needs 4 slices with 6 clock cycles latency(to achieve this I used a shift register, so that the synthesizer will understand to use the DSP slice's registers ). I was basically trying to do this in the following code, but I keep on getting zero definition of * error. What did I do wrong.

entity InferingTest is
	generic(dataWidth: integer:=35);
	port(
		en: in STD_LOGIC;
		CLK: in STD_LOGIC;
		A: in STD_LOGIC_VECTOR(dataWidth-1 downto 0);
		B: in STD_LOGIC_VECTOR(dataWidth-1 downto 0);
		P: out STD_LOGIC_VECTOR(2*dataWidth-1 downto 0)
	);
end InferingTest;

architecture Behavioral of InferingTest is
	constant latencyForDSP: integer:=5;
	type arr is array(latencyForDSP downto 0) of STD_LOGIC_VECTOR(2*dataWidth-1 downto 0);
	signal shiftReg: arr;
	signal PP: STD_LOGIC_VECTOR(2*dataWidth-1 downto 0);
begin
	
	P<=shiftReg(latencyForDSP);
	process(CLK)
	begin
		if(CLK'event and CLK='1') then 
			if(en='1') then 
				 PP<=A * B;	
				 shiftReg(0)<=PP;
				 shiftReg(1 to latencyForDSP)<=shiftReg(0 to latencyForDSP-1);	
			end if;
		end if;
	end process;

end Behavioral;

 

[axcdd]

You do it wrong. It's not about delaying the output. DSP48E is maximally 25 x 18 multiplayer. So your code will not be inffered as DSP48E.
Everything is described in UG191 page 71.

DSP1 = (0, A[16:0]) x (0, B[16:0]) 
DSP2 = (A[41:17] x (0, B[16:0])) 
+ PCIN shift17 of DSP1
DSP3 = ((0, A[16:0]) x B[4:17]) + 
PCIN of DSP2
DSP4 = (A[41:17] x B[35:17]) + PCIN 
shift17 of DSP3

 

[kommu4946]

I was basically trying to do this in the following code, but I keep on getting zero definition of * error. What did I do wrong.

you are performing multiplication with std_logic_vector data type,which is not supported in vhdl. Use numeric_std package which has unsigned and signed datatypes for arithmetic operations.
use type conversion for multiplication.

 

[SharpWeapon]

Yeah, I have seen the code in the UG193. But what does that mean then, I thought the synthesizer will cascade the respective slices accordingly right? How would you infer the four slices then, manually arranging the numbers as noted there?

The type conversion is not a problem, I just had in mind the DSP slice which handles two's compliment vectors.

 

[axcdd]

I got bad experience with xilinx dsp48A synthesizer, but i see that your code #1 with minor changes (std to signed) implemented well on spartan6

 

[SharpWeapon]

Oh, so did you actually get the four DSP48s inferred in the synthesis report?

 

[axcdd]

exactly:

DSP48A1 : 4
LUT : 29
Register : 87

@XC6SLX150T

 

[SharpWeapon]

Great! I also changed the numbers to signed, the synthesis works fine. While implementing I have this message, I am unable to see how it is implemented. Have you came across this massage by any chance?

Process "Synthesize - XST" completed successfully

Started : "Translate".
ERROR: could not find ngdbuild input file (ngc, ngo, or edif).

WARNING: could not find the netlist for the design, translate can not run.

 

[ads-ee]

Is there a ngd file for the design in the build directory after XST completes? There should be a file in the directory that ngdbuild leaves that will show you the command line used to call ngdbuild, make sure the ngd file it's looking for is correct.

 

[SharpWeapon]

Now it is working, thank you though.