[SOLVED] Inefficient LE usage for register implementation(quartus 2/cyclone 2)

[sensei616]

So I wrote a VHDL program for an 8-bit D-type register with several of the bits asynchronously clear and preset-able. Nothing wrong with the code and it compiles. When looking at the RTL viewer in quartus it looks as it should, however the logic element usage is 24, but I'd imagine it shouldn't be any more than 12, 8 LE's for the registers, and 4 for the asynchronous logic used. So I look at the Technology Map Viewer, which i assume shows the circuit at the logic element level, and it looks as though its not using the actual preset inputs on the logic element registers. Instead every bit that can be asynchronously controlled has its output tied to some large combination logic circuit, presumably to create the preset-able latch function, though I didn't quite figure out the logic of it.

Is there something wrong with my code, or can cyclone 2 logic elements not implement a synchronous D-type flip flop with both asynchronous preset and clear inputs? Thanks to anyone who can help me solve this mystery.

 

[FvM]

The problem is with the asynchronous preset. If you review the Cyclone II logic element description, you'll notice that they don't expose an asynchronous preset signal.

The register preset is achieved by using a NOT gate push-back technique. Cyclone II devices can only support either a preset or asynchronous clear signal.

To implement both clear and preset signals, or an asynchronous load of registers, Quartus uses an equivalent circuit with latches and XOR logic. It requires additional LEs and increases the propagation delay of the register's synchronous data path.

 

[sensei616]

Thanks for your answer. I'll have to look up logic elements more thoroughly next time.