Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
What's the problem?
Did you consider input impedance on load
Use CMOS unbuffered inverter or FET complementary buffer between stages.
Choose based on Vth and RdsOn. Or simply try a 15V logic gate.
BTW the RdsOn of an old technology CMOS inverter is around 500 ohms and with negative feedback becomes a linear amplifier.
Modern ones are low voltage are 25 ohms in 7 xxxALVC2 ? types. or the type used in MEGA chips.