latch will be introduced when you use reg in Verilog (as well as variable in VHDL) associated with output port and store the value arcording to the changing clock level(clk='1'). It's correct for both VHDL and Verilog.
latch will be infered when a combinational circuit described improperly
example:
1. when sensitivity list is not complete i.e all the combinational inputs must in sensitivity list
2. In always or process all the control paths are not evaluate the output