Re: In verilog what is the difference between using "always @" vs "@" on its own?
Realize that synthesis tools recognize patterns in the code you write and map those patterns into hardware. There may be more than one way to write your code that essentially describes the same functionality, but if the synthesis tool cannot recognize it, it can't map it to hardware.
There is no such thing as "@" on its own, and the example comments are not entirely correct.
@(expression) is a procedural statement that means "wait for a value change in the
expression". You need to know the context of where that statement is in order to know how it executes.
always statement; is an instantiation of a procedural process that begins at time 0, and when that statement completes, it repeats.
initial statement; is also an instantiation of a procedural process that begins at time 0, but when that statement completes, the process terminates.
You can executed multiple statements where one is required by surrounding it with
begin/end. In front of any procedural statement, you can put a @(expr) or #delay control that blocks execution of that statement. This code does not execute the block every clock cycle:
Code:
always @(posedge clk)
begin
A< = B;
@(posedge clk);
C <= D;
end
could also be written as
Code:
always
begin
@(posedge clk) A< = B;
@(posedge clk) C <= D;
end
And this block of code will take two clock cycles to complete. Each assignment occurs every other clock cycle.
However, most synthesis tools will not synthesize this because they allow only one "@" at the top of the block. More advanced behavioral synthesis tools can recognize this code.
A
forever is a procedural statement. it must be instantiated by an
initial or
always block. So initial forever @... is equivalent to always @... except that synthesis tools will not recognize it. Also, there are constructs in SystemVerilog that allow you to exit a
forever loop, but there is nothing that can terminate an
always block.