In verilog what is the difference between using "always @" vs "@" on its own?

[matrixofdynamism]

In verilog what is the difference between using "always @" vs "@" on its own?

The book states that "The @ symbol is used to specify an event control". It then gives the following examples:

​

@(clock) q = d; //q = d is executed whenever signal clock changes value

​

@(posedge clock) q = d; //q = d is executed whenever signal clock does a positive transition ( 0 to 1,x or z, // X to 1, z to 1 )

​

@(negedge clock) q = d; //q = d is executed whenever signal clock does a negative transition ( 1 to 0,x or z, X to 0, z to 0)

​

q = @(posedge clock) d; //d is evaluated immediately and assigned to q at the positive edge of clock

If this is possible then why do we write "always @"?

Finally how do these two compare with using the forever loop as in "forever @".

Is it that in synthesis code we can only used "always @" but all three of them basically do the same thing?

 

[ads-ee]

Re: In verilog what is the difference between using "always @" vs "@" on its own?

These are procedural statements:
@(posedge clock) q = d;
forever begin @(psedge clk) q = d; end

There is no such thing as a forever@ construct.

always blocks are not procedural therefore they can't exist in procedural code, i.e. like what is used for testbenches to drive stimulus. e.g.

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Code Verilog - [expand]
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initial begin  // module level construct
  a = 0;
  #300;
  a = 1;
  ...
  always@ ()...  // syntax error! always@ is not procedural code
  @(); // waits for whatever is called out in the sensitivity list before continuing
end

---

---

Code Verilog - [expand]
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@(clock) q = d; // not synthesizable as there are no registers that respond to both edges of the clock
// not synthesizable these are procedural statements.
@(posedge clock) q = d;
@(negedge clock) q = d;
q = @(posedge clock) d; // not synthesizable is a procedural statement
 
always @ (posedge clock) q <= d; // exists in the module context and is synthesizable requires sensitivity list to signal when it's executed.

---

 

[dave_59]

Re: In verilog what is the difference between using "always @" vs "@" on its own?

Realize that synthesis tools recognize patterns in the code you write and map those patterns into hardware. There may be more than one way to write your code that essentially describes the same functionality, but if the synthesis tool cannot recognize it, it can't map it to hardware.

There is no such thing as "@" on its own, and the example comments are not entirely correct.

@(expression) is a procedural statement that means "wait for a value change in the expression". You need to know the context of where that statement is in order to know how it executes.

always statement; is an instantiation of a procedural process that begins at time 0, and when that statement completes, it repeats. initial statement; is also an instantiation of a procedural process that begins at time 0, but when that statement completes, the process terminates.

You can executed multiple statements where one is required by surrounding it with begin/end. In front of any procedural statement, you can put a @(expr) or #delay control that blocks execution of that statement. This code does not execute the block every clock cycle:

always @(posedge clk) 
      begin
          A< = B;
          @(posedge clk);
          C <= D;
     end

could also be written as

always 
      begin
          @(posedge clk) A< = B;
          @(posedge clk) C <= D;
     end

And this block of code will take two clock cycles to complete. Each assignment occurs every other clock cycle.
However, most synthesis tools will not synthesize this because they allow only one "@" at the top of the block. More advanced behavioral synthesis tools can recognize this code.

A forever is a procedural statement. it must be instantiated by an initial or always block. So initial forever @... is equivalent to always @... except that synthesis tools will not recognize it. Also, there are constructs in SystemVerilog that allow you to exit a forever loop, but there is nothing that can terminate an always block.

 

[matrixofdynamism]

Re: In verilog what is the difference between using "always @" vs "@" on its own?

Thanks Dave, you have answered the question fully.