In IO pad, why do we need a floating Well?

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bluestatic

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A lot of IO design use floating Nwell on the PMOS output transistors. For input IO cell, I guess this is to do with 5V tolerance. But why do we need a floating Nwell in output cells.
Any one got a clear picture on this issue?
 

For 3.3Volt logic IO,s that need to be 5Volt tolerant, a way of ensuring that the PMOS gate oxide never sees 5.5Volts across it is to use floating wells.
 

**broken link removed**
 

For protecting the bonding wire connected with sub when bonding
 

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