In DC set_ip_delay or set_op_delay who & how decides val

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vlsi_maniac

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hi all,
while going through a tutorial on DC i got one doubt.
create_clock constraints clock to a frequency that design has to work.
but if we put set_input_delay who decides these factors.
since set_input_delay indicates time from input pad to input of FF on what factors we should decide these things.
thanks
 

Re: In DC set_ip_delay or set_op_delay who & how decides

Hi,

Input delay depends on the signal coming to your module from external world and similary output delau for output signals.

These delay indicates how much percentage of clock is required for external logic so that these signals will be stable for the module.

regards,
freak
 

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