Getting to zero in a PMOS pass transistor regulator may
require railing the gate. Doing this takes you way off the
linear range of the current mirror, in a simple design, and
so you'll see that referred back to a nonzero input offset
and a loss of regulation quality. You might set a minimum
load current or resistance. Or you might need a low side
shunt and run the output more like class AB (which can
also help with stability at light load, at the cost of
wasted power & design effort / sensitivity).
Load regulation at higher currents (or dropout) depends
a lot on just where you take your feedback and its
reference ground. Chip? Package post? Full remote?
Hundreds of mA and hundreds of mOhms, forget your
10mV accuracy.
Yeah, there's a slight possibility that simulation !=
reality. Or so I've heard. Whether that's reality's
problem, I doubt.