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In analog IC design, differences between Simulation and Measurement results?

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efficik

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Currently I work on a linear regulator design using CMOS technology.
I tried to extract the correct bonding and board resistances and do the layout simulation for the circuit.

But there are some difference between my simulation in cadence and measurement results in lab.

1. The dropout voltage in measurement is around 200mOhm higher than in the simulation.
2. The static load regulation from 0 to 1mA is much high in the measurement than in the simulation.
But from 1mA to 100mA the results match well >> this indicates that the bonding and board resistances I used in the simulation should be correct.

I am wondering if it is possible that the simulation model doesn't represent the reality in the silicon in some time?
Or the simulation and measurement should be 100% the same, it is only the problem of my own measurement error?
 

leo_o2

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1. Dropout difference might be caused by paraiste Resistance in layout. It needs R-extracting for post-layout simulation.
2. Load regulation might be caused by some current leakage in PCB board and IC.
 

dick_freebird

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Getting to zero in a PMOS pass transistor regulator may
require railing the gate. Doing this takes you way off the
linear range of the current mirror, in a simple design, and
so you'll see that referred back to a nonzero input offset
and a loss of regulation quality. You might set a minimum
load current or resistance. Or you might need a low side
shunt and run the output more like class AB (which can
also help with stability at light load, at the cost of
wasted power & design effort / sensitivity).

Load regulation at higher currents (or dropout) depends
a lot on just where you take your feedback and its
reference ground. Chip? Package post? Full remote?
Hundreds of mA and hundreds of mOhms, forget your
10mV accuracy.

Yeah, there's a slight possibility that simulation !=
reality. Or so I've heard. Whether that's reality's
problem, I doubt.
 

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