efficik
Newbie level 1
Currently I work on a linear regulator design using CMOS technology.
I tried to extract the correct bonding and board resistances and do the layout simulation for the circuit.
But there are some difference between my simulation in cadence and measurement results in lab.
1. The dropout voltage in measurement is around 200mOhm higher than in the simulation.
2. The static load regulation from 0 to 1mA is much high in the measurement than in the simulation.
But from 1mA to 100mA the results match well >> this indicates that the bonding and board resistances I used in the simulation should be correct.
I am wondering if it is possible that the simulation model doesn't represent the reality in the silicon in some time?
Or the simulation and measurement should be 100% the same, it is only the problem of my own measurement error?
I tried to extract the correct bonding and board resistances and do the layout simulation for the circuit.
But there are some difference between my simulation in cadence and measurement results in lab.
1. The dropout voltage in measurement is around 200mOhm higher than in the simulation.
2. The static load regulation from 0 to 1mA is much high in the measurement than in the simulation.
But from 1mA to 100mA the results match well >> this indicates that the bonding and board resistances I used in the simulation should be correct.
I am wondering if it is possible that the simulation model doesn't represent the reality in the silicon in some time?
Or the simulation and measurement should be 100% the same, it is only the problem of my own measurement error?