# [SOLVED]Imput impedance of a folded cascode

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#### prestonee

##### Full Member level 3
Input impedance of a folded cascode

Can anyone help me calculate the input impedance? with simulation I can measure a cap value much larger then the Cgs+ cgd+cgb caps . I realize there is a miller effect which i have as Cgd*(1+gm1*Rload), since this is the miller of the gate cap i assume rload would be the output impedance looking into the drain of the input device, not the output of the folded cascode. I need another set of eyes + math hands because my calculated total Gate cap is approx ~ 120fF. where Sim is showing around 1.5pF. factor of 10x....
I have the rload being aprox equal to rds/2 (input rds // with nsource rds). so I get total Cgate = Cgs + Cgd(1 + gm1*rds/2) + Cgb. Can anyone see an obvious error?

-Pb

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Ok I ended up solving this myself. When doing the math before I assumed that the impedance looking into the source of the nfet was 1/gm. however it is (1+z/rds)/(gm+gds) which.. is bigger then 1/gm therefor the output impedance of the cs amp which is part of the diff pair is in fact close in proximity to rds/2. which increased my input impedance to about 2pF. (a substantial cap) which in turn greatly affects my Beta in my closed loop calculations. This now agrees with my simulations.

-Pb

Dear Prestonee

there are tow kinds of input resistance and cpacitance specified by the foundries. these are the common mode and the differential mode. please tell which one you are interest in

Ok I ended up solving this myself. When doing the math before I assumed that the impedance looking into the source of the nfet was 1/gm. however it is (1+z/rds)/(gm+gds) which.. is bigger then 1/gm therefor the output impedance of the cs amp which is part of the diff pair is in fact close in proximity to rds/2. which increased my input impedance to about 2pF. (a substantial cap) which in turn greatly affects my Beta in my closed loop calculations. This now agrees with my simulations.

-Pb

I was trying to solve why my loopgain was much lower then expected, I designed a unique amplifier that basically is made of two parallel amplifiers of different topologies. I posted a question on here that gave me feedback correlating what I was expecting. After reading whitepapers on feed forward I agreed with the papers that I should expect an openloop gain of A + B. however my ac sims which sim loop gain were not summing when being simmed independent of eachother. I found that if i added buffers infront of the diff pairs they did add, I also found that my openloop gains in fact did add. So I believed there must be something affecting my Beta term, however the caps in the feedback network I was dealing with were in the order of 2 to 8 pF and so it was hard to believe I had such a large input cap that could overwhelm my closed loop beta. after various sims I concluded that one amplifiers input pair had an input impedance equal to about 200fF. which i expected, however my folded cascode which I also originally calculated to be around 300fF was simulating input impedance of 2pF. I had previous miscalculated the Ro when determining the miller affect of the gate cap of my input pair. It was actually much higher then I expected. And have discovered unintentionally that increasing the output impedance of the folded cascode(thereby increasing its gain) increases its gate capacitance(reducing loopgain) as a byproduct to the limit of rout being rds/2.
-Pb

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