reg Enable;
reg [31:0] A, B, DataOut, MultOut, AddOut;
wire [31:0] A, B;
always@(posedge clock)
if (Enable == 1) DataOut <= MultOut;
else DataOut <= AddOut;
[B]always@(posedge clock) begin
saveA <= A;
saveB <= B;
end
assign InA = Enable ? A : saveA;
assign InB = Enable ? B : saveB;
assign MultOut = InA * InB;[/B]
assign AddOut = A + B;
// dropping the save registers and replacing MultOUt inputs
with
// assign InA = Enable ? A : 32'h0;
// assign InB = Enable ? B : 32'h0;
// is viable too