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Dynamic power consumption.

Lívia_Reis

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I have two basic questions:

(1) If a basic D flip-flop has its clock gated-off, but it keeps "receiving" continuously toggling data at its D pin, will there be any dynamic power consumption? In such a (theoretical) scenario, would it make sense to also gate the D pin to logical 0 in order to reduce power?

dynamic_power_ff.png


(2) Which one does save more power? To gate-off the FF´s clock or to keep the FF in reset state? Or maybe both?
 

dick_freebird

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If you gate it off then you'll burn only static power when
idle, but now you toggle both that "gate" and the D input
when active.

In most modern DFFs the structure is tri-state inverter latches
(with set / reset injected by making some of them NAND or
NOR instead). D only toggles one inverter. CLK toggles many.
Reset does not stop CLK toggling all internal inverters, only
some.

A SPICE simulation from decent transistor level models would
be a good way to "what-if?" all of these various options.

A question is, how much power reduction is actually needed
and what's it worth to you in terms of -

- layout area
- design effort to add gingerbread
- simulation time to verify additional modes
- repeat last two until clean
- testability impact (can you test stopped-clock functionality
with decent coverage?)
 

Easy peasy

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if the clock is static, then the only additional power lost in the ckt in toto, is the capacitive loss in charging and discharging the D input capacitance - which is usually miminal ( Pdiss = Cgate . V^2 . Freq )
 

Lívia_Reis

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If you gate it off then you'll burn only static power when
idle, but now you toggle both that "gate" and the D input
when active.

In most modern DFFs the structure is tri-state inverter latches
(with set / reset injected by making some of them NAND or
NOR instead). D only toggles one inverter. CLK toggles many.
Reset does not stop CLK toggling all internal inverters, only
some.

A SPICE simulation from decent transistor level models would
be a good way to "what-if?" all of these various options.

A question is, how much power reduction is actually needed
and what's it worth to you in terms of -

- layout area
- design effort to add gingerbread
- simulation time to verify additional modes
- repeat last two until clean
- testability impact (can you test stopped-clock functionality
with decent coverage?)
Thanks!

"If you gate it off then you'll burn only static power when idle, but now you toggle both that "gate" and the D input when active." - but I never said both, I said D only. There would be any dynamic burn or it is associated with the CLK pin only?
--- Updated ---

if the clock is static, then the only additional power lost in the ckt in toto, is the capacitive loss in charging and discharging the D input capacitance - which is usually miminal ( Pdiss = Cgate . V^2 . Freq )
Ok, so there would be a dynamic power consumption even without clock, but it would be minimal? Is that it? Can you give me some percentage numbers? Not accurate, of course! Like:

dynamic_power_table.png


How would you guys rate this table in terms of % of dynamic power? Do you agree with my intuitive rating order (from max to min)? :)

Thanks a lot!
 
Last edited:

Lívia_Reis

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what is the input capacitance for the D input ... ? ( clue - read the data sheet )
Ah, this is just a theoretical question... just to have a clue of the answer. There is not a real DFF involved. :) But I´ll see if I can find some documentation or lib files with that kind of info for some modern cells... Thanks!
 

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