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Improving Power Consumption

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keyboardcowboy

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I came across a verilog example of improving power consumption in a multiplier. The original code is

Code:
reg Enable;
reg [31:0] A, B, DataOut, MultOut, AddOut;
wire [31:0] A, B;
always@(posedge clock)
if (Enable == 1) DataOut <= MultOut;
else DataOut <= AddOut;
assign MultOut = A * B;
assign AddOut = A + B;

The assumption is

"Assume that signal enable is active (high) 20% of the time. Assume the adder consumes too little power that it is not worth to consider it for power optimization."

The optimized solution given is

Code:
reg Enable;
reg [31:0] A, B, DataOut, MultOut, AddOut;
wire [31:0] A, B;
always@(posedge clock)
if (Enable == 1) DataOut <= MultOut;
else DataOut <= AddOut;

[B]always@(posedge clock) begin
saveA <= A;
saveB <= B;
end
assign InA = Enable ? A : saveA;
assign InB = Enable ? B : saveB;
assign MultOut = InA * InB;[/B]

assign AddOut = A + B;

// dropping the save registers and replacing MultOUt inputs
with
// assign InA = Enable ? A : 32'h0;
// assign InB = Enable ? B : 32'h0;
// is viable too

I do not understand the part in bold in the solution code. A and B are saved as saveA, and saveB, and the multiplier is still multiplying them irrespective of the enable signal. How does this save power?
 

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