Hi Steve,
Basically, verification is a difficult task, and there are more and more new tools,
languages, and techniques developed for it, making the technical berriers even
higher.
there are system level, chip level, and module level verifications. However,
I have some work experience with chip and module level verification. For functional verification, traditional methods are HDL test-bench based, you need
to know how to organize a verification environment using HDL. the two books
listed above are good ones to read, plus, you may find it good to know about
HDL API (VerilogPLI or VHDL FLI). However, it seems a transition to new techniques in functional verification, like HVLs(specman, vera), formal methods.
(it is said systemVerilog is good both for design and verification)
For system level, you may need an ESL, like SystemC or c/c++.
you may also need to know some script languages, like unix shell, perl, etc.