Important question on verification

[masai_mara]

Hi folks,
I am thinking of making a change in jobs. I have been working mainly on design and functional verification but almost all of them were on FPGA's. I now intend to go into ASIC design/verification. Could you people please point me out the necessary things to update myself on. I dont think it matters much for design but verification of asics invloves a lot more than those targeted for fpga's. I will appreciate any feedbacks on this aspect. does new methodologies like ABV or systemC matter much?? anything that I need to concentrate in particular?


thanks in advance for your replies,
steve

 

[gogogo]

some books are useful to you.
<< Writing Testbenches--Functional Verification of HDL Models>>
<<system on chip verification methology>> Kluwer

 

[realtek]

many different with FPGA ,
you need DC, PT,and write a lot of testbench
,model, call library, co-work with analog/layout team,
power issue, clock tree ........

(I suggest you should read synopsys SOLD (DC/PT part), better do some tutorial for beginning)


but it's more interesting when tapeout and IC works , good luck!!

 

[william_qiu]

Lots of things should be considered. The most important thing to be remebered is for FPGA you may change your design as will but for ASIC the chance will be rare.

 

[rprince006]

Hi Steve,

Basically, verification is a difficult task, and there are more and more new tools,
languages, and techniques developed for it, making the technical berriers even
higher.

there are system level, chip level, and module level verifications. However,
I have some work experience with chip and module level verification. For functional verification, traditional methods are HDL test-bench based, you need
to know how to organize a verification environment using HDL. the two books
listed above are good ones to read, plus, you may find it good to know about
HDL API (VerilogPLI or VHDL FLI). However, it seems a transition to new techniques in functional verification, like HVLs(specman, vera), formal methods.
(it is said systemVerilog is good both for design and verification)

For system level, you may need an ESL, like SystemC or c/c++.

you may also need to know some script languages, like unix shell, perl, etc.

 

[foster_cn]

for scripts, as rirince006 mentioned, TCL is also very important, especially for synopsys tools

 

[masai_mara]

Thanks for all the answers. I do know some scripting in TCL and have developed test benches mainly in VHDL for verification of module level blocks and also some chip level test benches for medium sized cores. So are there any major points to keep in mind when I shift to ASICS. what is the generally practiced mehtodology for verification of ASICS and how does it differ from FPGA's apart from being more rigorous. for example what sort of coverage do we aim for?

thanks,
steve

 

[rprince006]

Hi,

I have less knowledge about FPGA, and the difference between FPGA and ASIC.

Using HDL to write test-bench is a tranditional way, and it is difficult to cover all
functional tests with only hdl based metthds.

Basically, there are two kind of coverage: code coverage and functional coverage,
and you need specific tools to collect coverage info and evaluate your effort.

 

[Kulprashant]

hi,
Writing Testbenches--Functional Verification of HDL Models jarnick.

with regards,
kul

 

[mason_y]

Other useful book:
L. Bening, H. Foster, "Principles of Verifiable RTL Design", Kluwer Academic Publishers,. 2001, ISBN: 0792373685
good luck!

 

[sarath51]

If u'e concern is in verification it is better to focus on Systerm verilog where which has enhanced features for assertion new constructs for verification