import whole the truth table to the Quartus for Optmization

[Ata-Va]

How to Import whole the truth table into Quartus and automatically Optimize it

Hi every one
I had designed a Combinational circuit in Quartus II 13.0 but it was not optimized as the number of input variables were so many I couldn't simplify it using Karnaugh Maps ,so I decided to draw whole truth table on the schematic environment with out pre-simplification, as I searched on the net I found out that Quartus does the simplification by it self after compilation.

so after the compile I checked Netlist Viewers/technology map viewer(post filtering),I found the optimized circuit there ,I wonder if I can export or copy it from there and use it in schematic environment, on the other hand is there a way to import whole the truth table to the Quartus so that it automatically optimizes and makes logics by it self ?

I'd be glad for any sort of hint. thank you

 

[TrickyDicky]

Ususally, circuits are written in HDL, and often in behavioural form.
There is no way to input a K map, just the circuit diagram (which people dont use much, as it cannot be simulated directly). It is much better to use an HDL (VHDL or Verilog).

 

[Ata-Va]

well I know what you mean but as a matter of fact in next step I have to Implement Transistor level of my digital circuit in ADS Software and simulated the whole Analog and digital parts together, so I need the optimized version of my digital circuit Individually.

 

[TrickyDicky]

Well the you're looking at ASIC tools and Quartus probably wont be much help, as it does not implement gates, only LUTs.

 

[Ata-Va]

thx for reply dear TrickyDicky
well I don't think so as far as I know at least in ISE we can export the design for automatic lay-out and ASIC application so the software must be able to generate multi level logic gate for lay-out, I don't know whether Quartus supports this feature as ISE does.

 

[std_match]

Look at Logic Friday: http://sontrak.com/

 

[Ata-Va]

thx std_match it was very useful, it helped me alot
by the way, if you already used it,can you tell me that how much should I relay on the answers, I mean does the software has any bug resulting in a wrong answer?

 

[std_match]

can you tell me that how much should I relay on the answers, I mean does the software has any bug resulting in a wrong answer?

I don't know of any bugs, but in this case verification is much easier than synthesis. Just apply all possible input combinations and check that the output is correct.

 

[Ata-Va]

I don't know of any bugs, but in this case verification is much easier than synthesis. Just apply all possible input combinations and check that the output is correct.

And still 1 thing remains, I can not export the output in VHDL o Verilog Or block diagram format to Import Automatically to other software such as Advanced design system.