Feb 10, 2006 #1 A arunssn Newbie level 2 Joined Feb 10, 2006 Messages 2 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,305 how to implement equations in verilog that are synthesisable. for eg |p0 - q0| etc.
Feb 10, 2006 #2 eecs4ever Full Member level 3 Joined Jan 31, 2006 Messages 176 Helped 28 Reputation 56 Reaction score 10 Trophy points 1,298 Location Analog Environment Activity points 2,838 if p0 and p1 are 1 bit wires... wire out; assign out = p0 + p1; // assigns to out their sum assign out = p0 - p1; // difference assign out = p0 ^ p1; // ^ means xor , // this is equal to |p0 - q0| assign out = p0 && p1; // logical AND assign out = p0 || p1; // logical OR
if p0 and p1 are 1 bit wires... wire out; assign out = p0 + p1; // assigns to out their sum assign out = p0 - p1; // difference assign out = p0 ^ p1; // ^ means xor , // this is equal to |p0 - q0| assign out = p0 && p1; // logical AND assign out = p0 || p1; // logical OR
Feb 10, 2006 #3 A ami Member level 3 Joined Apr 28, 2005 Messages 61 Helped 4 Reputation 8 Reaction score 0 Trophy points 1,286 Location VN Activity points 1,952 Code: module eg(q0,q1,out); parameter BW = 8; input [BW-1:0] q0; input [BW-1:0] q1; output [BW-1:0] out; assign out = (q0>q1)? (q0-q1) : (q1-q0); enmodule
Code: module eg(q0,q1,out); parameter BW = 8; input [BW-1:0] q0; input [BW-1:0] q1; output [BW-1:0] out; assign out = (q0>q1)? (q0-q1) : (q1-q0); enmodule