implementing equations

[arunssn]

how to implement equations in verilog that are synthesisable.
for eg |p0 - q0| etc.

 

[eecs4ever]

if p0 and p1 are 1 bit wires...

wire out;

assign out = p0 + p1; // assigns to out their sum
assign out = p0 - p1; // difference
assign out = p0 ^ p1; // ^ means xor ,
// this is equal to |p0 - q0|

assign out = p0 && p1; // logical AND
assign out = p0 || p1; // logical OR

 

[ami]

module eg(q0,q1,out);
parameter BW = 8;
input [BW-1:0] q0;
input [BW-1:0] q1;
output [BW-1:0] out;
assign out = (q0>q1)? (q0-q1) : (q1-q0);
enmodule