Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Implementation of FPGA in asynchronous enviroment

Not open for further replies.


Newbie level 4
Aug 16, 2007
Reaction score
Trophy points
Activity points
This is the thing. Our design is asynchronous, memories, CPUs, everything. But in future we must move on to FPGA, mostly because of our need to implement a CPU in FPGA. So do you have any idea how to do this? How to implement something that should be synchronous (FPGA design) in a completely asynchronous environment? Is there anything I should know? Is it possible?

I'm working in transport industry, so having as few as possible clocks is desirable.
How is it done?

While moving AsynctoSync, signals cross clock domains, and these crossings are very important and should be dealt in a very specilized way. more can be read at my posts:


Why use an asynchronous CPU? What goals are you hoping to achieve?

How about using a conventional well-optimized CPU core such as the Xilinx MicroBlaze, or better yet select an FPGA with an embedded microprocessor such as the Xilinx Virtex-4 with PowerPC?

Transport industry -- do you mean trains, ships, planes, and trucks? Why do they care about number of clocks?

yes.. trains mostly.. and also powerplants...

and asynchronous CPU.. well it's not up to me... that is dictated by others...

Added after 7 minutes:

I guess they care about the number of clocks because of routing PCBs. Honestly, I'm relatively new to his, just got out of university.

Added after 6 minutes:

it's not that we have GALS system, but system that is not clock driven, but level driven I guess... and soon we will be forced to use fpga, among others to implement that asynchronous CPU into fpga, cause it is obsolete.. we use VME bus.. so.. asynchronous :( well problems exist to be solved :) so my hope will never die :)

Added after 2 minutes:

so what to do this.. in this mostly asynchronous world... what to do what to do....

Added after 2 minutes:

and minimization of clock line due to power consumption.. i guess

Added after 31 minutes:

has anybody here worked on a similar projects? maybe I will be out of job here, if it is totally wrong to try to implement PLDs in such environment.. :) don't let me :) it is one of rare positions in my country to work on this.. and i love this :)

leeloothedolphin said:
and asynchronous CPU.. well it's not up to me... that is dictated by others...

You should not have problems with asynchronous SRAMs. As they are passive devices, you can totally control them with synchronous design. If they're still using core memory, same thing - except you'll need to deal with the peculiarities of reading/writing them.

Do your CPU designs use any kind of clocking?

If they do, there actually is a high degree of synchronous design. They probably don't use edge-triggered FF's, but that doesn't mean the designs are asynchronous. Only the components are asynchronous.

The FPGAs I work with have FFs with both asynchronous sets and resets, in addition to the edge-sensitive clock signal. So if your design is full of RS FFs, you can ignore the clock input. You will probably need to "create" (actually allocate) FFs with a "primitive component", rather than with behavioral HDL code.

If you are using an old-school multiple clock design, you can generate them with synchronous design from a single clock source. If two clocks can change at roughly the same time, you will need to be careful at clock boundaries. Because you don't have total control of the geometry, differing routing delays can cause unpredictable overlap (or nonoverlap).

If you decide to redesign with edge-triggered design, you can build a CPU that uses only a single clock. There is an internal clock network that is optimized to minimize skew - all edge-triggered FFs change at roughly the same time. The compactness of the FPGA allows this. With logic spread out over several chips, it is much harder to build a reliable system that uses a single clock that drives edge-triggered FFs.

Not open for further replies.

Part and Inventory Search

Welcome to