Implement carrier detection logic in FPGA

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pulkit.vlsi

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Hi,
I am working on an application where i need to implement carrier sense logic for and half duplex 10Base2 interface.

in one ieee document i got below detail:


Please help me understand this logic.
 

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Ethernet PHY involves analog functions that can't be implemented with FPGA digital IO. How are you interfacing FPGA to 10BASE2 media?
 

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FPGA will deal with digital part only. One side it is connected to MAC. other side it is connected to transformer which is further connected to a 10 base 2 transiver IC.
 

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Which transceiver? Which signals are connecting the transceiver to FPGA? CRS generation is usually part of ethernet transceiver PHY.
 

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Carrier sense detection for 10BASE2 is performed in PLS unit, see 802.3 section 1 clause 7. Mentioned CRS signal is used e.g. in 10BASE-T.
--- Updated ---

You are quoting new 10BASE-T1S spec (single twisted pair ethernet), a completely different technology.
 
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