Implement ARM cores on a FPGA chip?

[LucienZ]

Hi everyone, I am a master student and this is my first post on this
forum. My research group is looking for a multicore embedded platform
for deploying an in-house developed computer vision algorithm. I've
checked some available development boards and now still weigh the
ideas in my mind.

One solution that interests me is 'synthesizable' processor cores on a
FPGA chip, where I can parallelize the data processing on different
cores. As far as I know, this solution is based on 'synthesizable'
soft-cores, e.g. MicroBlaze, Nios or ARM Cortex-M1 etc. But I've seen
one design article (carried out at NXP, the Netherlands) that claims
they have implemented two ARM926EJ-S processors on a Xilinx Virtex 4
FPGA chip. I am wondering what technologies enable this
implementation.

My current knowledge only reaches the level of HDL-based hardware
design on FPGAs (and some higher abstraction levels concerning
software), but I am not very familiar with the 'macrocells', 'hard
core IP' and digital ASIC design. I see some Virtex 4 products come
with embedded hard PowerPC blocks, but I have not seen ARM...So I
would like to ask you experienced scientists these questions:

1. How to implement one or more such ARM926EJ-S cores on a FPGA chip
(detailed information on the NXP design article is not available)? I
need some key words in this field and better with some recommended
design articles.
2. How to interpret the word 'synthesizable' with respect to soft-
cores and macrocells, respectively?
3. If someone has experiences on multicore parallel processing
development, I would be grateful if you can suggest some nice
development platforms (real-time performance is our top concern).
Probably I need to make a new post later describing the requirements…

Thanks very much for your attention!
Lucien

 

[mobile-it]

check this: http://www.actel.com/products/mpu/cortexm1/default.aspx

 

[ram]

HI,

for your first question -
The ARM926EJS is processor from arm which is ARM9. Here the "S" in name indicates that it is synthesizable means it is RTL (verilog) code of ARM9. So it can be synthesized to FPGA or to any techmonilgy library.

 

[kel8157]

For free processors I can recommend you took look on 8051 delton project. I have palyed a bit with it:
CPU 8051 translation from VHDL to verilog. I used 8051 from...
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There is also LEON a processor from ESA: Idid a few projected and posted on my site. Example :The LEON2-XST model includes one optional PCI interface: a simple target-only interface. The interface is developed primarily to support DSU communications over the PCI bus. Focus has been put on small area and robust operation....
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Regarding ARM. I worte a debuf monitor for AHB:The following will show a simple AHB monitor. The monitor can be applied to any AHB bus to debug the activity of the bus....
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You also might want to look on :
The flow is from C code or assembly into VERILOG READMEMHEX format....
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we never fail to see this post.. haha.. :|