i already attached the whole code for CPU but here is the RAM code
module RAM (Q,D,addr,we,clk);
input [7:0] D;
input [7:0] addr;
input we,clk;
output [7:0] Q;
wire high;
assign high=1;
lpm_ram_dq myRAM (.q(Q),.data(D),.address(addr),.we(we),.inclock(clk),.outclock(high));
defparam myRAM.lpm_width=8;
defparam myRAM.lpm_widthad=8;
defparam myRAM.lpm_indata="REGISTERED";
defparam myRAM.lpm_outdata="UNREGISTERED";
defparam myRAM.lpm_file="RAMtest.mif";
endmodule
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can u check for me whether it is internal RAM or not?