CPU @ RTL Design - Verilog (with complete documentation)

[yahootew3000]

cpu design verilog

Introduction To The Design of CPU using RTL Approach.
This CPU is a simple 8-bit processor with 8-bit address bus. The architecture is based on accumulator-based design. The instruction set is grouped into few categories which is shown as below:

1. Data manipulation
a. ADD X Add the value in memory to the accumulator.
b. SUB X Subtract the value in memory to the accumulator.
c. XOR X Exclusive-OR logic operation value in memory to the accumulator.
d. AND X Perform AND logic operation value in memory to the accumulator.
e. ADR Add between registers.

2. Data transfer
a. MVI Move the immediate data to the specified register.
b. MVD Move the specified memory data to the specified register.
c. MOV Move data between registers.
d. LDA X Load the memory data to the accumulator.
e. STA X Load the accumulator to the memory data.

3. Program control
a. BRN X Branch if the value in the accumulator is negative.
b. JMP X Jump to a specified address.

6. Shifting
a. SHR Shift one bit of the register to the right.
b. SHL Shift one bit of the register to the left.

5. Miscellaneous
a. HALT Stay no operation.
b. NOP No operation until next instruction.

The design is using the Λltera Quαrtus II 7.2

 

[yahootew3000]

open core for picoblaze

 

[Eiffel.Z]

simple cpu verilog

yahootew3000
excuse me, I have no enough point to download the files. so can you mail these files to me? Thank you very much!
E-mail: yikoulian2001@126.com

best regards
Eiffel

 

[master_picengineer]

rapidshare verilog risc

Yes, this is too expensive. Please share it with Rapid share.
Thanks.

 

[echo47]

kcpsm3.zip

All attached files are copied to the free mirror server about once per month, so it should happen soon.
Then you can download from the free mirror without using any points.

 

[yahootew3000]

design simple cpu using verilog

Yes, this is too expensive. Please share it with Rapid share.
Thanks.

You can choose to download the documentation instead. The codes are included as well. The Verilog files are for your convenience

Added after 3 minutes:

I have included the winrar format, it is less in size compared to the winzip format. Both are the same.

 

[RegUser_2]

simple cpu in verilog

For extra examples of CPU designs for FPGA, some can take a look at opencores.org (various RISC designs and popular PIC and AVR CPU cores what makes them very attractive because the software developments suites already exists).

Then some can also take look on the CIRCUIT CELLAR articles (ie issue 116 March 2000 Building a RISC System in an FPGA where all the gory story of developing both a 16-bit RISC and adapting retrgetable LCC compiler are described and source code is given).

Both Xilinx and LATTICE provide free optimized 8-bit CPU cores sources (PICOBLAZE and MACO8). PICOBLAZE description are all over the net and there is ongoing PACOBLAZE project which adds various perifery to the core and makes it less vendor dependent.

 

[Eiffel.Z]

verilog documentation and2

yahootew3000
Hi, brother. I have a question when I simulate your code given to me. My tools is QII 5.0, and the RAM ipcore transfer result is not the same as your document mentioned. When read RAM, the Data of RAM may be appear at the next edge of the clock, there are some problem.
and I refer to the RAM Megafunction User Guide from Altera Website. The actual working operation is as my simulate status, so how you get the document result?

 

[Johnson]

16-bit picoblaze

"Both Xilinx and LATTICE provide free optimized 8-bit CPU cores sources (PICOBLAZE and MACO8). PICOBLAZE description are all over the net and there is ongoing PACOBLAZE project which adds various perifery to the core and makes it less vendor "

They do not give you the main source code, so you can not do change on them.

8-bit address is very short address space, can you change it to 16-bit?

Based on what processor this one is designed? Also is it a RISC one?

 

[RegUser_2]

how to design a simple processor in verilog

"Both Xilinx and LATTICE provide free optimized 8-bit CPU cores sources (PICOBLAZE and MACO8). PICOBLAZE description are all over the net and there is ongoing PACOBLAZE project which adds various perifery to the core and makes it less vendor "

They do not give you the main source code, so you can not do change on them.

8-bit address is very short address space, can you change it to 16-bit?

Based on what processor this one is designed? Also is it a RISC one?

ALL of them are RISC, ALL of them contain source code (optimized for FPGA families)

PACOBLAZE is less optimized but more universal

https://bleyer.org/pacoblaze/

 

[Johnson]

cpu design with verilog

What about IDE and compiler suuport? Is assembler included?

 

[salma ali bakr]

nnarm assembler

"Both Xilinx and LATTICE provide free optimized 8-bit CPU cores sources (PICOBLAZE and MACO8). PICOBLAZE description are all over the net and there is ongoing PACOBLAZE project which adds various perifery to the core and makes it less vendor "

They do not give you the main source code, so you can not do change on them.

8-bit address is very short address space, can you change it to 16-bit?

Based on what processor this one is designed? Also is it a RISC one?

ALL of them are RISC, ALL of them contain source code (optimized for FPGA families)

PACOBLAZE is less optimized but more universal

https://bleyer.org/pacoblaze/

so can i find easily the verilog source code of picoblaze on the net...?
not just diagrams..!!
do you have any sites that you use already for this...
thank youuuuuu

 

[echo47]

kcpsm3.v

Verilog and VHDL source code for PicoBlaze is downloadable from the Xilinx PicoBlaze lounge. You may need to register and login, but it's free. Look for files kcpsm3.v or kcpsm3.vhd in the ZIP archive.
https://www.xilinx.com/ipcenter/processor_central/picoblaze/member/
https://www.xilinx.com/ipcenter/processor_central/picoblaze/member/KCPSM3.zip

However, the source code contains many instantiated Xilinx flop and LUT primitives, so don't expect it to be easy to understand or easy to use with a non-Xilinx FPGA. It may have been hand-coded or translated from some other language.

 

[Johnson]

design simple processor+verilog+fpga

Verilog and VHDL source code for PicoBlaze is downloadable from the Xilinx PicoBlaze lounge. You may need to register and login, but it's free. Look for files kcpsm3.v or kcpsm3.vhd in the ZIP archive.
https://www.xilinx.com/ipcenter/processor_central/picoblaze/member/
https://www.xilinx.com/ipcenter/processor_central/picoblaze/member/KCPSM3.zip

However, the source code contains many instantiated Xilinx flop and LUT primitives, so don't expect it to be easy to understand or easy to use with a non-Xilinx FPGA. It may have been hand-coded or translated from some other language.

The xilinx wesite do not give you the source file! What you can get is just synthesized netlist and you can not modify or customize it!

 

[echo47]

a simple processor design in verilog

Did you try downloading the file and looking inside? One Xilinx web page even says, "PicoBlaze for Spartan-3 design files now includes source Verilog and VHDL."

The code is at LUT/flop level, so it's difficult to understand, but the the author's comments say he did it that way on purpose.

 

[Johnson]

processor verilog rtl code

We use "source code" for codes at high level and before synthesis, not "The code is at LUT/flop level", YOU CAN NOT EDIT IT!

 

[echo47]

rtl design with d register

People sometimes write original code at the LUT/flop level, even though it's tedious work. In this message, the PicoBlaze author explains a little why he did it that way:
http://forums.xilinx.com/xlnx/board/message?board.id=PicoBlaze&message.id=68&query.id=2313#M68

The PicoBlaze code is editable, but it wouldn't be any fun. In this message, the author suggests editing the code to add a feature, but advises that it won't be easy:
http://forums.xilinx.com/xlnx/board/message?board.id=PicoBlaze&message.id=23&query.id=2289#M23

 

[RegUser_2]

mico32 instruction set assembly

Lattice distributes free MICO8 and MICO32 RISC cores with verilog sourve code. MICO32 is a high performance 32-bit RISC system which already got ported to other vendors FPGA's (Spartan 3). It's code is not specific to any FPGA vendor, except for the Lattice specific JTAG core. It implements wishbone internal bus what makes it easy to incorporate other open cores. MICO32 have GCC C compiler devised for it's software development

There are ARM clones (nnARM) and OpenRISC (OR1200) cores some can find on the web.

All this at the top of various cores of popular PIC and AVR 8-bit clones available on the opencores.org site.

 

[Johnson]

rtl approach in verilog

Is there any unified software and hardware development environment for Lattice cpu core?

 

[guoshaojun]

verilog simple cpu

this is too expensive. Please share it with Rapid share.
Thanks.