Impedance matching in LVDS signalling

[YUV]

Re: LVDS Signalling

I used Cyclone II in my designs. But as a receiver in multi-drop applications: one source and two receivers.
Unfortunately, I found that Cyclone was very sensitive. I terminated cable on the far end with 100 Ohm resistors. But anyway I couldn't get a proper working untill I put termination resistors on each input of Cyclone (each board). So the cable was terminated twice and amplitude of signal dropped down because of load, but Cyclones began to work much more reliable.
How did you terminate your board?

 

[Acido Cinico]

Re: LVDS Signalling

I've used standard 100 ohm resistors as
terminators.
Now I'm trying with a multidrop configuration
and I'm having better results.
Maybe it was an issue due to saturation of the
LVDS differential inputs of the PLL. Having
a multidrop configuration or a total impedance
that is lower than 100ohm help reducing
the peak-to-peak clock input at the PLL.

 

[YUV]

Re: LVDS Signalling

I imitated Natinal's 386th LVDS receiver in Cyclone II, 4 chanels * 7bit. But I didn't use one of bits. It always had a zero level.
I found that very often PLL tells that it's locked, but the mentioned bit pulsed. I think the problem is in a data alignment.
I created a simple circuit that checked "rx_locked" output of ALTLVDS megafunction and state of the bit. If PLL is locked and the bit is zero (I calculated several pulses), than OK. Else reset signal is generated and feed to "pll_areset" input of ALTLVDS. That eliminated the problem comletely.