Re: LVDS Signalling
I imitated Natinal's 386th LVDS receiver in Cyclone II, 4 chanels * 7bit. But I didn't use one of bits. It always had a zero level.
I found that very often PLL tells that it's locked, but the mentioned bit pulsed. I think the problem is in a data alignment.
I created a simple circuit that checked "rx_locked" output of ALTLVDS megafunction and state of the bit. If PLL is locked and the bit is zero (I calculated several pulses), than OK. Else reset signal is generated and feed to "pll_areset" input of ALTLVDS. That eliminated the problem comletely.