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Impact of contamination for CMOS process

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Junior Member level 2
Jan 5, 2011
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Russia, Moscow
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Hi! One of the most unclear questions about CMOS process for me are

1) Which operations are the most sensetive for contamination? Is it forming of gate oxyde & gate itself - so that minimum contamination is just above and below gate oxide... ?
2) What is acceptable level of contamination and which are the usual sources of such contamination in production?

Would be glad to hear any answers or hints :)

The most important thing is a thickness of gate oxide. If a thickness of oxide will vary then transistor will have another threshold voltage. In factory where manufacturing IC the most important problem the control of growing oxide level. the gate itself in not so problem, the gate is poly silicious or metal. of course the thickness of gate is also play the rule in characteristic of MOS transistor. So most important to control the oxide level, if between the oxide level and p sub there is a contamination, this also will change the threshold voltage of transistor.

Etch / clean prior to thin ox growth is a big deal. But
there's plenty of ways to kill an integrated circuit, the
transistors being only a few steps of many.

You can have "contamination" from all kinds of things.
Even photoresist polymerization from deep UV / soft
X-Ray, poisoning the bottom of vias.

I don't think sensitivity is the point. There's only one
right answer, "none". And there's only one practical
reality, "as little as possible". The real trick is in
determining what it is, where it came from and how
it goes away and doesn't come back.

I see... Could you suggest any book about "ways of killing IC" or tell some more about it? :)

Still actual :)
Now I understand why Na (and other high-mobility ions) is so dangerous.
Still interesting to know maximum allowable concentration & how well Cl passivates them.

Other contaminants are also interesting :)

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