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Illegal section pin value - OrCAD Design Entry CIS

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damian_s

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illegal section pin value

Dear all,

When I tried to generate netlist for (Allegro) PCB Editor, I had this messages :

Loading... E:\DAMIAN_S\ KULIAH\TESIS\ BOARD_DESIGN\ CYCLONEIII\ SKEMATIK\ NETLIST_VER1_ REPLACED_ COMP/pstxnet. dat
packaging the design view...Illegal section pin value
Illegal section pin value
Illegal section pin value
Illegal section pin value
......

Does anyone know what it means? is it an error or just warnings?

FYI, the netlist is successfully generated and I can do import netlist in Allegro PCB Editor, but I'm still curious about the messages

best regard,
damian_s
 

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