library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity timer is
port( input : in std_logic;
output : out time );
end timer;
architecture Behavioral of timer is
begin
p1 : process (input)
variable time1, time2, time3 : time := 0 ns;
begin
if (input'event and input = '1') then
time2 := now;
elsif (input'event and input = '0') then
time1 := now;
time3 :=time2-time1;
end if;
output <= time3;
end process p1;
end behavioral;