ihave errors {timer in vhdl code},,(can anyone help me)

[sherifhansol]

always it gives me error in that code & can any one help me even with giving other codes for timer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity timer is
port( input: in std_logic;
output: out time );
end timer;
architecture Behavioral of timer is
begin
p1rocess
variable time_elapsed: time:=0ns ;
begin
wait until input'event and input='1';
loop
wait until (input'event and input='0');
time_elapsed := input'last_event;
output <= time_elapsed;
end loop;
end process p1;
end behavioral ;

 

[mendozaulises]

You have not declared anything in the sensitivity list of process p1. I think input must be included in sensitivity list.
What other errors are you getting?

 

[nand_gates]

Its not clear whats ur intension is? If you want to measure time
between two rising edges of inout signal then here is the code!

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity timer is
  port( input             : in  std_logic;
        output            : out time );
end timer;
architecture Behavioral of timer is
  signal time1, time2 : time := 0 ns;
begin
  p1 : process (input)
  begin
     if (input'event and input = '1') then
       time2 <= time1;
       time1 <= now;
     end if;
  end process p1;
  output <= time1 - time2;
end behavioral;

 

[gck]

The code given for measuring time between rising & falling edges using NOW is not synthsizable.

need to use some referance higher frequency clock, for timing measurment,

 

[xstal]

Hi,
I guess he wants to measure time between the rising and the falling edges of the input. i.e. the width of the high pusle of input.

library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
use IEEE.STD_LOGIC_ARITH.all; 
use IEEE.STD_LOGIC_UNSIGNED.all; 
entity timer is 
  port( input             : in  std_logic; 
        output            : out time ); 
end timer; 
architecture Behavioral of timer is 
begin 
  p1 : process (input)
    variable time1, time2, time3 : time := 0 ns; 
  begin 
     if (input'event and input = '1') then 
       time2 := now; 
     elsif (input'event and input = '0') then 
       time1 := now;
       time3 :=time2-time1; 
     end if;
     output <= time3;  
  end process p1; 
end behavioral;

Added after 1 minutes:

this is of course not synthesizable

Added after 3 minutes:

correction

time3:=time1-time2;[/code]