You can not have a conditional port in VHDL. You could create your own preprocessor, but that is outside of VHDL.
If you want a solution in VHDL, I suggest that you put a default value on the input port and combine it with a enable/disable generic.
For synthesis, you use the generic so the input port is never used. It will then be optimized away by the synthesis tool. The default value makes it possible to omit the port without errors when you instantiate the entity for synthesis.
Don't rely on default values for input ports that are used in the synthesized code. It is OK in simulation, but I don't know if any synthesis tool will do what you want (connect the input to a fixed value).
Don't rely on default values for input ports that are used in the synthesized code. It is OK in simulation, but I don't know if any synthesis tool will do what you want (connect the input to a fixed value).
I once tried it, since I thought it could work. I got into some problems, so I decided that I should never waste time on it again. Unfortunately, I don't remember any details of the problem.
Maybe a default value on an input port is like a default value for a signal without a register, it is ignored for synthesis?
Anyone having some spare time to test this?
I once tried it, since I thought it could work. I got into some problems, so I decided that I should never waste time on it again. Unfortunately, I don't remember any details of the problem.
Maybe a default value on an input port is like a default value for a signal without a register, it is ignored for synthesis?
Anyone having some spare time to test this?
Maybe a default value on an input port is like a default value for a signal without a register, it is ignored for synthesis?
Anyone having some spare time to test this?
There can be no doubt that unconnected signals with a default value are propagated as constants into the design and all logic depending on it will be removed as far as possible. A disadvantage is that you get a bunch of compiler warnings about constant signals.