ifdef at the port side equivalent in vhdl

[imbichie]

Hi All,

Is there any way to replace the ifdef at the port side in VHDL.
Foe example, if my dut in verilog is like this

module wb_ram
(
    input  wire [31:0]   dat_i;
    output wire [31:0]   dat_o;
    input  wire [31:0]   adr_i;
    input  wire          we_i;
    input  wire [3:0] 	 sel_i;
    input  wire   		 cyc_i;
    input  wire   		 stb_i;
    output reg 		     ack_o;
[B] `ifdef CTI[/B]
    input  wire [2:0] 	 cti_i;
[B] `endif[/B]

    input  wire     	 clk_i;
    input  wire     	 rst_i
);

but my Testbench is in VHDL, in VHDL ifdef won't support,
so if i am instantiate this DUT in the testbench, how to replace the ifdef at the port side.

During the component declaration also we need to take care of the ifdef

 

[TrickyDicky]

use generics. `ifdef is not really recommended for verilog anymore, you should use parameters instead.

 

[std_match]

You can not have a conditional port in VHDL. You could create your own preprocessor, but that is outside of VHDL.
If you want a solution in VHDL, I suggest that you put a default value on the input port and combine it with a enable/disable generic.

For synthesis, you use the generic so the input port is never used. It will then be optimized away by the synthesis tool. The default value makes it possible to omit the port without errors when you instantiate the entity for synthesis.

Don't rely on default values for input ports that are used in the synthesized code. It is OK in simulation, but I don't know if any synthesis tool will do what you want (connect the input to a fixed value).

 

[FvM]

Don't rely on default values for input ports that are used in the synthesized code. It is OK in simulation, but I don't know if any synthesis tool will do what you want (connect the input to a fixed value).

I don't see why it should not work in synthesis, except for top entities where input ports connect to real hardware inputs.

 

[std_match]

I don't see why it should not work in synthesis, except for top entities where input ports connect to real hardware inputs.

I once tried it, since I thought it could work. I got into some problems, so I decided that I should never waste time on it again. Unfortunately, I don't remember any details of the problem.

Maybe a default value on an input port is like a default value for a signal without a register, it is ignored for synthesis?
Anyone having some spare time to test this?

 

[TrickyDicky]

I once tried it, since I thought it could work. I got into some problems, so I decided that I should never waste time on it again. Unfortunately, I don't remember any details of the problem.

Maybe a default value on an input port is like a default value for a signal without a register, it is ignored for synthesis?
Anyone having some spare time to test this?

I would also be very surprised - all of the megafunctions that altera generate have deafult values on all of their ports - including the clock!

 

[FvM]

Maybe a default value on an input port is like a default value for a signal without a register, it is ignored for synthesis?
Anyone having some spare time to test this?

There can be no doubt that unconnected signals with a default value are propagated as constants into the design and all logic depending on it will be removed as far as possible. A disadvantage is that you get a bunch of compiler warnings about constant signals.